1. Field of the Invention
The invention concerns a device for justifying at regular intervals a digital bit stream made up of frames received on a first synchronous link timed by a first clock and to be sent on a second synchronous link timed by a second clock. The present invention can be applied to a gateway between two links within the same synchronous digital hierarchy network.
2. Description of the prior art
In this type of network digital bit streams are formed according to the synchronous multiplexing hierarchy defined in CCITT Recommendations G.707, G.708 and G.709. A digital bit stream, with a bit rate of 155 Mbit/s, for example, is made up of frames called synchronous transport modules structured in octets. Each module can be represented as an array having 270 columns and 9 rows. Each of the 9 rows can be regarded as a packet of 270 octets, including a header on nine octets and a payload on 261 octets. Each payload comprises data which is part of a data container known as a virtual container. There are several types of virtual container. Each virtual container includes a path overhead reserved for network management purposes and data.
The number of data bits conveyed in each virtual container is the same for all containers of the same type. On the other hand, the position of the containers relative to the frames is not fixed, because of phase differences due to propagation times in the network and because of positive or negative justification carried out at the network nodes. As a result, a container can straddle two consecutive modules. The header of the first row of a module is used to detect the start of the module. This does not usually coincide with the start of a virtual container. The start of a virtual container is identified by a pointer transmitted in the header of a specific row of each module.
When the digital bit stream is stored in a memory, the value of this pointer enables relative addressing of the information constituting the start of a container relative to the address at which the pointer is stored. The pointer is followed by a block of three spare octets which can be used for negative justification. This entails sending the data with an advance of three octets by using the three spare octets to send three data ochers, rather than three meaningless octets.
Positive justification entails sending the data with an advance of three octets by sending, after the three spare octets, three octets having no meaningful content, rather than three data octets, and by shifting the data so that there is always the same number of data octets in the container in question. One use of this positive or negative justification facility in a gateway connecting a plesiochronous network to a synchronous digital hierarchy network is to convert from a bit rate of 144 Mbit/s to a bit rate of 155 Mbit/s. It is also used to compensate phase differences between two synchronous links connected by a gateway within the same synchronous digital hierarchy network.
A gateway of this type includes a buffer memory whose capacity is very much less than one frame. The data, without the headers, is written into the buffer at the timing rate of a first clock which times the first link; it is read out at the timing rate of a second clock which times the second link. The difference between the current write address and the current read address of this memory is determined in order to find out how full the buffer is with data waiting to be read. This difference is compared to a first threshold value close to the capacity of the buffer to command positive justification if it exceeds this first threshold value. It is also compared to a second threshold value to command negative justification if it is less than the second threshold value. These two threshold values are fixed.
For a given frequency difference between the first and second clocks, this device supplies a periodic signal to command either positive or negative justification. For example, each period of this signal commands 87 consecutive justifications at regular intervals plus an empty interval having a duration equivalent to three justifications. A frequency difference of 5 ppm, for example, corresponds to a period of 30 ms for the justification control signal, i.e. a frequency in the order of 33 Hz.
If the digital bit stream passes through three gateways in succession, on leaving the third gateway the signal can feature 3.times.87 consecutive justifications followed by an empty interval whose duration is equivalent to 3.times.3 justifications in each period of the signal. This irregular justification is no problem in a synchronous digital hierarchy but produces phase jitter if the digital bit stream enters a plesiochronous network. This jitter can be filtered, but the lower the frequency the more difficult is it to filter the jitter.
An object of the invention is to facilitate this filtering by reducing this jitter at source, i.e. at each gateway through which the digital bit stream passes.